TPS562210A, TPS563210A Datasheet by Texas Instruments

V'.‘ ‘F. B X E I TEXAS INSTRUMENTS
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Efficiency (%)
Output Current (A)
Vout = 5V
Vout = 3.3V
Vout = 1.8V
C015
VOUT
TPS562210A
TPS563210A
VOUT
VIN
EN
VIN
VBST
SW
GND
EN
VFB
1
2
3
7
5
6
PG
4SS
8
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS562210A
,
TPS563210A
SLVSDP9 –NOVEMBER 2016
TPS56x210A, 4.5-V to 17-V Input, 2-A, 3-A Synchronous Step-Down Voltage Regulator
In 8-Pin SOT-23
1
1 Features
1• TPS562210A: 2-A Converter With Integrated
133-mΩand 80-mΩFETs
• TPS563210A: 3-A Converter With Integrated
68-mΩand 39-mΩFETs
• D-CAP2™ Mode Control for Fast Transient
Response
• Advanced Eco-mode™ Pulse-skip
• Input Voltage Range: 4.5 V to 17 V
• Output Voltage Range: 0.76 V to 7 V
• 650-kHz Switching Frequency
• Low Shutdown Current Less than 10 µA
• 1% Feedback Voltage Accuracy (25°C)
• Startup from Pre-Biased Output Voltage
• Cycle By Cycle Over-current Limit
• Hiccup-mode Under Voltage Protection
• Non-latch OVP, UVLO and TSD Protections
• Adjustable Soft Start
• Power Good Output
2 Applications
• Digital TV Power Supply
• High Definition Blu-ray Disc™ Players
• Networking Home Terminal
• Digital Set Top Box (STB)
3 Description
The TPS562210A and TPS563210A are simple,
easy-to-use, 2-A, 3-A synchronous step-down
converters in 8 pin SOT-23 package.
The devices are optimized to operate with minimum
external component counts and optimized to achieve
low standby current.
These switch mode power supply (SMPS) devices
employ D-CAP2™ mode control providing a fast
transient response and supporting both low
equivalent series resistance (ESR) output capacitors
such as specialty polymer and ultra-low ESR ceramic
capacitors with no external compensation
components.
The devices operate in Advanced Eco-mode™, which
maintains high efficiency during light load operation.
The TPS562210A and TPS563210A are available in
a 8-pin 1.6 × 2.9 (mm) SOT (DDF) package, and
specified from –40°C to 85°C of ambient temperature.
Device Information(1)
ORDER NUMBER PACKAGE BODY SIZE (NOM)
TPS562210A DDF(8) 1.60 mm × 2.90 mm
TPS563210A
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Spacer
Spacer Simplified Schematic Efficiency
l TEXAS INSTRUMENTS
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TPS562210A
,
TPS563210A
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 5
6.7 Typical Characteristics.............................................. 6
7 Detailed Description............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ...................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
8 Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1 Device Support .................................................... 23
11.2 Related Links ........................................................ 23
11.3 Receiving Notification of Documentation Updates 23
11.4 Community Resources.......................................... 23
11.5 Trademarks........................................................... 23
11.6 Electrostatic Discharge Caution............................ 23
11.7 Glossary................................................................ 23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
DATE REVISION NOTES
November 2016 * Initial release.
l TEXAS INSTRUMENTS I: :l I: :l I: :l
SW
VBST
VFB
GND
2
3
1
EN
6
8
7
VIN
45
SS
PG
3
TPS562210A
,
TPS563210A
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5 Pin Configuration and Functions
DDF Package
8 Pin
Top View
Pin Functions
PIN DESCRIPTION
NAME NO.
GND 1 Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit. Connect
sensitive VFB to this GND at a single point.
SW 2 Switch node connection between high-side NFET and low-side NFET.
VIN 3 Input voltage supply pin. The drain terminal of high-side power NFET.
PG 4 Power good open drain output
SS 5 Soft-start control. An external capacitor should be connected to GND.
VFB 6 Converter feedback input. Connect to output voltage with feedback resistor divider.
EN 7 Enable input control. Active high and must be pulled up to enable the device.
VBST 8 Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between VBST and SW pins.
l TEXAS INSTRUMENTS
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,
TPS563210A
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
TJ= -40°C to 150°C (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage range
VIN, EN –0.3 19 V
VBST –0.3 25 V
VBST (10 ns transient) –0.3 27.5 V
VBST (vs SW) –0.3 6.5 V
VFB, PG –0.3 6.5 V
SS –0.3 5.5 V
SW –2 19 V
SW (10 ns transient) –3.5 21 V
Operating junction temperature, TJ–40 150 °C
Storage temperature, Tstg –55 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V
6.3 Recommended Operating Conditions
TJ= –40°C to 150°C (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage range 4.5 17 V
VIInput voltage range
VBST –0.1 23 V
VBST (10 ns transient) –0.1 26 V
VBST(vs SW) –0.1 6 V
EN –0.1 17 V
VFB, pg –0.1 5.5 V
SS –0.1 5 V
SW –1.8 17 V
SW (10 ns transient) –3.5 20 V
TAOperating free-air temperature –40 85 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) TPS562210A TPS563210A UNIT
DDF (8 PINS)
RθJA Junction-to-ambient thermal resistance 106.1 87.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 49.1 41.6 °C/W
RθJB Junction-to-board thermal resistance 10.9 14.6 °C/W
ψJT Junction-to-top characterization parameter 8.6 4.7 °C/W
ψJB Junction-to-board characterization parameter 10.8 14.6 °C/W
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(1) Not production tested.
6.5 Electrical Characteristics
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVIN Operating – non-switching supply current VIN current, TA= 25°C, EN = 5V, VFB = 0.8 V 190 290 µA
IVINSDN Shutdown supply current VIN current, TA= 25°C, EN = 0 V 3.0 10 µA
LOGIC THRESHOLD
VENH EN high-level input voltage EN 1.6 V
VENL EN low-level input voltage EN 0.6 V
REN EN pin resistance to GND VEN = 12 V 225 450 900 kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
VFB threshold voltage TPS562210A TA= 25°C, VO= 1.05 V, IO= 10 mA, Eco-mode™
operation 772 mV
VFB threshold voltage TPS562210A and
TPS563210A
TA= 25°C, VO= 1.05 V 758 765 772
mVTA= 0°C to 85°C, VO= 1.05 V(1) 753 777
TA= -40°C to 85°C, VO= 1.05 V(1) 751 779
IVFB VFB input current VFB = 0.8 V, TA= 25°C 0 ±0.1 µA
MOSFET
RDS(on)h High side switch resistance TA= 25°C, VBST – SW = 5.5 V, TPS562210A 133 mΩ
TA= 25°C, VBST – SW = 5.5 V, TPS563210A 68
RDS(on)l Low side switch resistance TA= 25°C, TPS562210A 80 mΩ
TA= 25°C, TPS563210A 39
CURRENT LIMIT
IOCL Current limit(1) DC current, VOUT = 1.05 V , L1 = 2.2 µH, TPS562210A 2.5 3.2 4.3 A
DC current, VOUT = 1.05 V , L1 = 1.5 µH, TPS563210A 3.5 4.2 5.3
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold(1) Shutdown temperature 155 °C
Hysteresis 35
SOFT START
ISS SS charge current VSS = 1.2 V 4.2 6 7.8 µA
POWER GOOD
VTHPG PG threshold VFB rising (Good) 85% 90% 95%
VFB falling (Fault) 85%
IPG PG sink current PG = 0.5 V 0.5 1 mA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP Output OVP threshold OVP Detect 125%x
Vfbth
VUVP Output UVP threshold Hiccup detect 65%x
Vfbth
tHiccupOn Hiccup Power On Time Relative to soft start time 1 cycle
tHiccupOff Hiccup Power Off Time Relative to soft start time 7 cycles
UVLO
UVLO UVLO threshold Wake up VIN voltage 3.45 3.75 4.05 V
Hysteresis VIN voltage 0.13 0.32 0.55
6.6 Timing Requirements
MIN TYP MAX UNIT
ON-TIME TIMER CONTROL
tON On time VIN = 12 V, VO= 1.05 V 150 ns
tOFF(MIN) Minimum off time TA= 25°C, VFB = 0.5 V 260 310 ns
l TEXAS INSTRUMENTS 100
C015
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10
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30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Efficiency (%)
Output Current(A)
Vout = 3.3V
Vout = 1.8V
C016
C013
C014
C011
C012
6
TPS562210A
,
TPS563210A
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6.7 Typical Characteristics
6.7.1 TPS562210A Characteristics
VIN = 12 V (unless otherwise noted)
Figure 1. Supply Current vs Junction Temperature Figure 2. VIN Shutdown Current vs Junction Temperature
Figure 3. VFB Voltage vs Junction Temperature Figure 4. EN Current vs EN Voltage
Figure 5. Efficiency vs Output Current
VI= 5 V
Figure 6. Efficiency vs Output Current
l TEXAS INSTRUMENTS
C017
C018
7
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,
TPS563210A
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TPS562210A Characteristics (continued)
Figure 7. Switching Frequency vs Input Voltage Figure 8. Switching Frequency vs Output Current
l TEXAS INSTRUMENTS
C023
C024
C021
C022
C019
C020
8
TPS562210A
,
TPS563210A
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6.7.2 TPS563210A Characteristics
VIN = 12V (unless otherwise noted)
Figure 9. Supply Current vs Junction Temperature Figure 10. VIN Shutdown Current vs Junction Temperature
Figure 11. VFB Voltage vs Junction Temperature Figure 12. EN Current vs EN Voltage
Figure 13. Efficiency vs Output Current
VI= 5 V
Figure 14. Efficiency vs Output Current
l TEXAS INSTRUMENTS
C025
C026
9
TPS562210A
,
TPS563210A
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TPS563210A Characteristics (continued)
Figure 15. Switching Frequency vs Input Voltage Figure 16. Switching Frequency vs Output Current
l TEXAS INSTRUMENTS U— E] V D fig, 1 [j 4‘ x E} .fi ’4H 2% [II BCL ZC
2 SW
ZC
XCON
PWM
Control Logic
+
+
+
UVP
OVP
3VIN
Ton
One-Shot
8VBST
+
6
VFB
OCL
+
+
Soft Start
7
EN
HS
LS
1 GND
SS
Voltage
Reference Ref
Hiccup
VUVP
VOVP
OCL
threshold
Regulator
UVLO
VREG5
VREG 5
TSD
5SS
4
PG
VTHPG
+
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7 Detailed Description
7.1 Overview
The TPS562210A and TPS563210A are 2-A, 3-A synchronous step-down converters. The proprietary D-CAP2™
mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic
capacitors without complex external compensation circuits. The fast transient response of D-CAP2™ mode
control can reduce the output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
TEXAS INSTRUMENTS Iss
FBTH
Css V 0.86
Tss(ms) Iss
´ ´
=
11
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,
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7.3 Feature Description
7.3.1 The Adaptive On-Time Control and PWM Operation
The main control loop of the TPS562210A and TPS563210A are adaptive on-time pulse width modulation (PWM)
controller that supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive
on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component
count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at
the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control.
7.3.2 Soft Start and Pre-Biased Soft Start
The TPS562210A and TPS563210A have adjustable soft-start. When the EN pin becomes high, the SS charge
current (ISS) begins charging the capacitor which is connected from the SS pin to GND (CSS). Smooth control of
the output voltage is maintained during start up. The equation for the soft start time, Tss is shown in Equation 1.
(1)
where VFBTH is 0.765 V and Iss is 6 µA.
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.3 Power Good
The power good output, PG is an open drain output. The power good function becomes active after 1.7 times
soft-start time. When the output voltage becomes within –10% of the target value, internal comparators detect
power good state and the power good signal becomes high. If the feedback voltage goes under 15% of the target
value, the power good signal becomes low.
7.3.4 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over
current condition exists consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing
the available output current. When a switching cycle occurs where the switch current is not above the lower OCL
threshold, the counter is reset and the OCL threshold is returned to the higher value.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time
(typically 14 µs) and re-start after the hiccup time.
When the over current condition is removed, the output voltage returns to the regulated value.
l TEXAS INSTRUMENTS SW
( )
IN OUT OUT
OUT(LL)
SW IN
V V V
1
I2 L f V
- ´
= ´
´ ´
12
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Feature Description (continued)
7.3.5 Over Voltage Protection
TPS562210A and TPS563210A detect over voltage condition by monitoring the feedback voltage (VFB). When
the feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high
and the high-side MOSFET is turns off. This function is non-latch operation.
7.3.6 UVLO Protection
Under voltage lock out protection (UVLO) monitors the internal regulator voltage. When the voltage is lower than
UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.7 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 155°C),
the device is shut off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Advanced Eco-Mode™ Control
The TPS562210A and TPS563210A are designed with Advanced Eco-mode™ to maintain high light load
efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and
eventually comes to point that its rippled valley touches zero level, which is the boundary between continuous
conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor
current is detected. As the load current further decreases the converter runs into discontinuous conduction mode.
The on-time is kept almost the same as it was in the continuous conduction mode so that it takes longer time to
discharge the output capacitor with smaller load current to the level of the reference voltage. This makes the
switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The transition
point to the light load operation IOUT(LL) current can be calculated in Equation 2.
(2)
l TEXAS INSTRUMENTS L flu H P P f l
P
OUT OUT
1
F
2 L C
=
p ´
OUT
R1
V 0.765 1
R2
æ ö
= ´ +
ç ÷
è ø
10µF
C3
22µF
C6
22µF
C7
L1 2.2uH
10µF
C2
0.1µF
C1
10.0k
R2
3.74k
R1
0.1µF
C5
22µF
C8
10.0kR3
GND 1
SW 2
VIN
3
PG 4
SS
5VFB 6
EN
7
VBST 8
U1
TPS562210A
8200pF
C4
100k
R4
VIN = 4.5 - 17 V VOUT = 1.05 V, 2 A
VOUT
EN
VIN
PG
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS562210A and TPS563210A are typically used as step down converters, which convert a voltage from
4.5 V to 17 V to a lower voltage. Webench software is available to aid in the design and analysis of circuits.
8.2 Typical Application
8.2.1 Typical Application, TPS562210A
4.5-V to 17-V Input, 1.05-V Output Converter.
Figure 17. TPS562210A 1.05V/2A Reference Design
8.2.1.1 Design Requirements
For this design example, use the parameters shown in Table 1.
Table 1. Design Parameters
PARAMETER VALUES
Input voltage range 4.5 V to 17 V
Output voltage 1.05 V
Output current 2 A
Output voltage ripple 20 mVp-p
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
To improve efficiency at light loads consider using larger value resistors, too high of resistance are more
susceptible to noise and voltage errors from the VFB input current are more noticeable.
(3)
8.2.1.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
(4)
l TEXAS INSTRUMENTS
( )
OUT IN OUT
CO(RMS)
IN O SW
V V V
I12 V L ƒ
´ -
=´ ´ ´
2 2
LO(RMS) O P P
1
I I I
12 -
= + l
P P
PEAK O
I
I I
2
-
= +
l
l
IN(MAX) OUT
OUT
P P
IN(MAX) O SW
V V
V
IV L ƒ
-
-
= ´
´
l
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off
at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of
Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the high
frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values
recommended in Table 2.
Table 2. TPS562210A Recommended Component Values
Output Voltage (V) R2 (kΩ) R3 (kΩ)L1 (µH) C6 + C7 + C8 (µF)
MIN TYP MAX
1 3.09 10.0 1.5 2.2 4.7 20 - 68
1.05 3.74 10.0 1.5 2.2 4.7 20 - 68
1.2 5.76 10.0 1.5 2.2 4.7 20 - 68
1.5 9.53 10.0 1.5 2.2 4.7 20 - 68
1.8 13.7 10.0 1.5 2.2 4.7 20 - 68
2.5 22.6 10.0 2.2 3.3 4.7 20 - 68
3.3 33.2 10.0 2.2 3.3 4.7 20 - 68
5 54.9 10.0 3.3 4.7 4.7 20 - 68
6.5 75 10.0 3.3 4.7 4.7 20 - 68
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
(5)
(6)
(7)
For this design example, the calculated peak current is 2.34 A and the calculated RMS current is 2.01 A. The
inductor used is a TDK CLF7045T-2R2N with a peak current rating of 5.5 A and an RMS current rating of 4.3 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS562210A and
TPS563210A are intended for use with ceramic or other low ESR capacitors. Recommended values range from
20µF to 68µF. Use Equation 8 to determine the required RMS current rating for the output capacitor.
(8)
For this design, two TDK C3216X5R0J226M 22 µF output capacitors are used. The typical ESR is 2 mΩeach.
The calculated RMS current is 0.286A and each output capacitor is rated for 4A.
8.2.1.2.3 Input Capacitor Selection
The TPS562210A and TPS563210A require an input decoupling capacitor and a bulk capacitor is needed
depending on the application. A ceramic capacitor over 10 µF is recommended for the decoupling capacitor. An
additional 0.1 µF capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The
capacitor voltage rating needs to be greater than the maximum input voltage.
l TEXAS INSTRUMENTS mo mo Twme : 1 usec / aw
Input Voltage (V)
Line Regulation (%)
4 6 8 10 12 14 16 18
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
D010
V = 50 mV / div (ac coupled)
I
Time = 1 µsec / div
SW = 5 V / div
I = 2 A
O
Output Current (A)
Load Regulation (%)
0 0.5 1 1.5 2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D008
Output Current (A)
Load Regulation (%)
0 0.5 1 1.5 2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D009
Output Current (A)
Efficiency (%)
0 0.5 1 1.5 2
0
10
20
30
40
50
60
70
80
90
100
D006
VIN = 5V
VIN = 12V
Output Current (A)
Efficiency (%)
0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 455
0
10
20
30
40
50
60
70
80
90
100
D007
VIN = 5V
VIN = 12V
15
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,
TPS563210A
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8.2.1.2.4 Bootstrap capacitor Selection
A 0.1µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
8.2.1.3 Application Curves
The following application curves were generated using the application circuit of Figure 17.
Figure 18. TPS562210A Efficiency Figure 19. TPS562210A Light Load Efficiency
Figure 20. TPS562210A Load Regulation, VI= 5 V Figure 21. TPS562210A Load Regulation, VI= 12 V
Figure 22. TPS562210A Line Regulation Figure 23. TPS562210A Input Voltage Ripple
l TEXAS INSTRUMENTS JWJLULM Tlme = 5 msec / aw Time :1 uses/aw WWW” H H fl Time :1 uses/aw Time = 200 usec / dw
VI = 10V/ div
SS = 5V/ div
VO = 500mV/ div
PG = 1V/ div
Time = 1 msec / div
EN = 10V/ div
SS = 5V/ div
VO = 500mV/ div
PG = 1V/ div
Time = 1 msec / div
V = 20 mV / div (ac coupled)
O
Time = 1 µsec / div
SW = 5 V / div
I = 2 A
O
V = 50 mV / div (ac coupled)
O
Time = 200 µsec / div
I = 500 mA / div
O
Load step = 0.5 A - 1.5 A
Slew rate = 500 mA / µsec
V = 20 mV / div (ac coupled)
O
Time = 1 µsec / div
SW = 5 V / div
I = 200 mA
O
V = 20 mV / div (ac coupled)
O
Time = 5 msec / div
SW = 5 V / div
I = 0 A
O
16
TPS562210A
,
TPS563210A
SLVSDP9 –NOVEMBER 2016
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Figure 24. TPS562210A Output Voltage Ripple Figure 25. TPS562210A Output Voltage Ripple
Figure 26. TPS562210A Output Voltage Ripple Figure 27. TPS562210A Transient Response
Figure 28. TPS562210A Start Up Relative To VIFigure 29. TPS562210A Start Up Relative To En
l TEXAS INSTRUMENTS
VI = 10V/ div
SS = 5V/ div
VO = 500mV/ div
PG = 1V/ div
Time = 5 msec / div
EN = 10V/ div
SS = 5V/ div
VO = 500mV/ div
PG = 1V/ div
Time = 5 msec / div
17
TPS562210A
,
TPS563210A
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Figure 30. TPS562210A Shut Down Relative To VIFigure 31. TPS562210A Shut Down Relative To EN
l TEXAS INSTRUMENTS
IN(MAX) OUT
OUT
P P
IN(MAX) O SW
V V
V
IV L ƒ
-
-
= ´
´
l
10µF
C3
22µF
C6
22µF
C7
L1 1.5uH
10µF
C2
0.1µF
C1
10.0k
R2
3.74k
R1
0.1µF
C5
22µF
C8
10.0kR3
GND 1
SW 2
VIN
3
PG 4
SS
5VFB 6
EN
7
VBST 8
U1
TPS563210A
8200pF
C4
100k
R4
VIN = 4.5 - 17 V VOUT = 1.05 V, 3 A
VOUT
EN
VIN
PG
18
TPS562210A
,
TPS563210A
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8.2.2 Typical Application, TPS563210A
4.5-V To 17-V Input, 1.05-V Output Converter.
Figure 32. TPS563210A 1.05 V / 3A Reference Design
8.2.2.1 Design Requirements
For this design example, use the parameters shown in Table 3.
Table 3. Design Parameters
PARAMETER VALUE
Input voltage range 4.5 V to 17 V
Output voltage 1.05 V
Output current 3 A
Output voltage ripple 20 mVpp
8.2.2.2 Detailed Design Procedures
The detailed design procedure for TPS563210A is the same as for TPS562210A except for inductor selection.
8.2.2.2.1 Output Filter Selection
Table 4. TPS563210A Recommended Component Values
Output Voltage (V) R2 (kΩ) R3 (kΩ)L1 (µH) C6 + C7 + C8 (µF)
MIN TYP MAX
1 3.09 10.0 1.0 1.5 4.7 20 - 68
1.05 3.74 10.0 1.0 1.5 4.7 20 - 68
1.2 5.76 10.0 1.0 1.5 4.7 20 - 68
1.5 9.53 10.0 1.0 1.5 4.7 20 - 68
1.8 13.7 10.0 1.5 2.2 4.7 20 - 68
2.5 22.6 10.0 1.5 2.2 4.7 20 - 68
3.3 33.2 10.0 1.5 2.2 4.7 20 - 68
5 54.9 10.0 2.2 3.3 4.7 20 - 68
6.5 75 10.0 2.2 3.3 4.7 20 - 68
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 9,
Equation 10 and Equation 11. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
ƒSW.
Use 650 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 10 and the RMS
current of Equation 11.
(9)
TEXAS INSTRUMENTS mo mo
Output Current (A)
Load Regulation (%)
0 0.5 1 1.5 2 2.5 3
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D003
Output Current (A)
Load Regulation (%)
0 0.5 1 1.5 2 2.5 3
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
D004
Output Current (A)
Efficiency (%)
0 0.5 1 1.5 2 2.5 3
0
10
20
30
40
50
60
70
80
90
100
D001
VIN = 5V
VIN = 12V
Output Current (A)
Efficiency (%)
0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 455
0
10
20
30
40
50
60
70
80
90
100
D002
VIN = 5V
VIN = 12V
l
2 2
LO(RMS) O P P
1
I I I
12 -
= +
l
lP P
PEAK O
I
I I
2
-
= +
19
TPS562210A
,
TPS563210A
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SLVSDP9 –NOVEMBER 2016
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Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
(10)
(11)
For this design example, the calculated peak current is 3.505 A and the calculated RMS current is 3.014 A. The
inductor used is a TDK CLF7045T-1R5N with a peak current rating of 7.3-A and an RMS current rating of 4.9-A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS563209 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20 μF to 68 μF. Use Equation 7
to determine the required RMS current rating for the output capacitor. For this design three TDK
C3216X5R0J226M 22 μF output capacitors are used. The typical ESR is 2 mΩeach. The calculated RMS
current is 0.292A and each output capacitor is rated for 4 A.
8.2.2.3 Application Curves
The following application curves were generated using the application circuit of Figure 32.
Figure 33. TPS563210A Efficiency Figure 34. TPS563210A Light Load Efficiency
Figure 35. TPS563210A Load Regulation, VI= 5 V Figure 36. TPS563210A Load Regulation, VI= 12 V
l TEXAS INSTRUMENTS WWW [ «1 Twme :1 use: / aw ,ML Tlme : 5 msec / aw Tlme :1 use: / dw ‘1 [ _f—_\_ Tlme :1 use: / dw Tlme : 200 usec / dw
V = 20 mV / div (ac coupled)
O
Time = 1 µsec / div
SW = 5 V / div
I = 3 A
O
V = 50 mV / div (ac coupled)
O
Time = 200 µsec / div
I = 1 A / div
O
Load step = 0.75 A - 2.25 A
Slew rate = 500 mA / µsec
V = 20 mV / div (ac coupled)
O
Time = 1 µsec / div
SW = 5 V / div
I = 300 mA
O
V = 20 mV / div (ac coupled)
O
Time = 5 msec / div
SW = 5 V / div
I = 0 A
O
Input Voltage (V)
Line Regulation (%)
4 6 8 10 12 14 16 18
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
D005
V = 50 mV / div (ac coupled)
I
Time = 1 µsec / div
SW = 5 V / div
I = 3 A
O
20
TPS562210A
,
TPS563210A
SLVSDP9 –NOVEMBER 2016
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Figure 37. TPS563210A Line Regulation Figure 38. TPS563210A Input Voltage Ripple
Figure 39. TPS563210A Output Voltage Ripple Figure 40. TPS563210A Output Voltage Ripple
Figure 41. TPS563210A Output Voltage Ripple Figure 42. TPS563210A Transient Response
l TEXAS INSTRUMENTS
VI = 10V/ div
SS = 5V/ div
VO = 500mV/ div
PG = 1V/ div
Time = 5 msec / div
EN = 10V/ div
SS = 5V/ div
VO = 500mV/ div
PG = 1V/ div
Time = 5 msec / div
VI = 10V/ div
SS = 5V/ div
VO = 500mV/ div
PG = 1V/ div
Time = 1 msec / div
EN = 10V/ div
SS = 5V/ div
VO = 500mV/ div
PG = 1V/ div
Time = 1 msec / div
21
TPS562210A
,
TPS563210A
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Figure 43. TPS563210A Start Up Relative To VIFigure 44. TPS563210A Start Up Relative To EN
Figure 45. TPS563210A Shut Down Relative To VIFigure 46. TPS563210A Shut Down Relative To EN
9 Power Supply Recommendations
The TPS562210A and TPS563210A are designed to operate from input supply voltage in the range of 4.5 V to
17 V. Buck converters require the input voltage to be higher than the output voltage for proper operation. The
maximum recommended operating duty cycle is 65%. Using that criteria, the minimum recommended input
voltage is VO/ 0.65.
Vias to the
internal SW
node copper
EN
VFB
VBST
GND
SW
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
VIN
GND
BOOST
CAPACITOR
OUTPUT
INDUCTOR
OUTPUT
CAPACITOR
VOUT
INPUT BYPASS
CAPACITOR
VIN
SW node copper
pour area on internal
or bottom layer
Additional
Vias to the
GND plane
HIGH FREQUENCY
INPUT BYPASS
CAPACITOR
Vias to the
internal SW
node copper
SS PG
SLOW START
CAPACITOR
VIA TO INTERNAL
GROUND PLANE
PG PULL UP
RESISTOR
POWER GOOD
TO PG PULL
UP VOLTAGE
TPS56x10A
22
TPS562210A
,
TPS563210A
SLVSDP9 –NOVEMBER 2016
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10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
l TEXAS INSTRUMENTS
23
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,
TPS563210A
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11 Device and Documentation Support
11.1 Device Support
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
TPS562210A Click here Click here Click here Click here Click here
TPS563210A Click here Click here Click here Click here Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
D-CAP2, Eco-mode, E2E are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS562210ADDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 2210A
TPS562210ADDFT ACTIVE SOT-23-THIN DDF 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 2210A
TPS563210ADDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 3210A
TPS563210ADDFT ACTIVE SOT-23-THIN DDF 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 3210A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Diameter AD Dimension designed to accommodate the component Width ED Dimension destgned to accommodate the componenl tengtn K0 Dimension designed to accommodate the component thickness 7 W OveraH wtdlh loe earner tape i P1 Pitch between SucCeSSWe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS562210ADDFR SOT-
23-THIN DDF 8 3000 180.0 9.5 3.17 3.1 1.1 4.0 8.0 Q3
TPS562210ADDFT SOT-
23-THIN DDF 8 250 180.0 9.5 3.17 3.1 1.1 4.0 8.0 Q3
TPS563210ADDFR SOT-
23-THIN DDF 8 3000 180.0 9.5 3.17 3.1 1.1 4.0 8.0 Q3
TPS563210ADDFT SOT-
23-THIN DDF 8 250 180.0 9.5 3.17 3.1 1.1 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Jul-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS562210ADDFR SOT-23-THIN DDF 8 3000 184.0 184.0 19.0
TPS562210ADDFT SOT-23-THIN DDF 8 250 184.0 184.0 19.0
TPS563210ADDFR SOT-23-THIN DDF 8 3000 184.0 184.0 19.0
TPS563210ADDFT SOT-23-THIN DDF 8 250 184.0 184.0 19.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Jul-2020
Pack Materials-Page 2
DDF0008A / —— \ JI- \ /~x
www.ti.com
PACKAGE OUTLINE
C
TYP
2.95
2.65
1.1 MAX
6X 0.65
8X 0.4
0.2
2X
1.95
TYP
0.20
0.08
0 - 8 0.1
0.0
0.25
GAGE PLANE
0.6
0.3
A
NOTE 3
2.95
2.85
B1.65
1.55
4222047/B 11/2015
SOT-23 - 1.1 mm max heightDDF0008A
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 4.000
DDF0008A
www.ti.com
EXAMPLE BOARD LAYOUT
(2.6)
8X (1.05)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4222047/B 11/2015
SOT-23 - 1.1 mm max heightDDF0008A
PLASTIC SMALL OUTLINE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
1
45
8
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
DDF0008A
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
6X (0.65)
8X (0.45)
8X (1.05)
(R ) TYP0.05
4222047/B 11/2015
SOT-23 - 1.1 mm max heightDDF0008A
PLASTIC SMALL OUTLINE
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
IMPORTANT NOTICE AND DISCLAIMER
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