The original VIPer IC is a monolithic single-chip, with the control section and power transistor sharing the same silicon die. VIPerPlus is a system on package, with a die using BCD6 technology for the control section and with vertical technology based on ST’s SuperMESH for the power section. The monolithic design of the original VIPer set limits on the complexity of the control section. In VIPerPlus, the dual-die architecture enables the control section to implement mixed analog and digital technology, along with computing capabilities of much higher density. Voltage breakdown has been boosted from the VIPer’s 700V up to 900V for VIPerPlus. Standby power is now lower than 30mW, which is not only compliant, but goes beyond the most stringent energy saving regulations, including the very demanding Japanese regulations. VIPerPlus supports the fixed-frequency PWM controls of the original VIPer and adds jittering and power boost. It also offers a quasi-resonant topology.