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dsPIC33 includes Direct Memory Access (DMA) controller for efficient data movement. The devices include eight DMA channels. Each of the eight channels can move data to/from eight different peripheral source or destinations. A simple arbitration scheme prioritizes each channel should more than one channel attempt transactions at the same time. The channel with the lower number wins. Note that the DMA system has its own bus for DMA transactions. This “backside” bus means that DMA transactions can occur simultaneously with CPU transactions. It is not necessary to disrupt the CPU operation or wait for a “dead cycle” in the CPU operation.
PTM Published on: 2011-11-07
New Zealand