The hibernation module operates on its own clock domain. As shown in the functional block diagram on this slide, it consists of a battery-backed memory, a low battery detection circuit, and power sequence logic. It also has a mechanism to generate interrupts to the CPU. Power to the hibernation module is supplied through VBAT pin which can be directly connected to an external battery or a regulated external power supply. In order to use the hibernation module, a 32.768 kHz single ended clock source, or a 32.768 kHz external crystal is required. The clock source can be connected to XOSC0 pin, leaving XOSC1 pin disconnected, or an external crystal can be connected to XOSC0 and XOSC1 pins. The buffered version of the 32.768 khz clock is available on the RTCCLK pin. In addition to low battery detection and RC match, the processor can wake up based on an external wake signal which can be supplied to the hibernation module through WAKE terminal. Also, HIB pin is provided to indicate the current state of the processor, i.e., if the processor is in hibernation mode or not.