The hibernation module also includes a real-time clock that consists of a 32-bit seconds counter and a 15-bit sub-seconds counter. The clock signal from the 32.768 kHz hibernation oscillator provides the clock source for the RTC. A buffered version of the 32.768 kHz signal is available on the RTCCLK output. The RTC counters are reset when the hibernation module is reset. The hibernation module also includes a 32-bit match register and a 15-bit field (RTCSSM) in the HIBRTCSS register that are compared to the value of the RTC 32-bit counter and 15-bit sub-seconds counter. The processor can be programmed to wake from hibernation mode when a match occurs, and generate an interrupt. The match interrupt generation takes priority over the interrupt clear.