This slide reviews the third mode of operation, deep sleep mode, which is used to further reduce the overall power consumption by turning off the clock to the processor and memory, i.e., Flash and SRAM along with the main oscillator and PLL. The active peripherals, i.e., the ones that are enabled in DCGC register can be clocked using the internal oscillator. This mode is used in applications where the processor does not need to be running code, and peripherals are able to function at a speed lower than run mode system speed. The device enters deep sleep mode if SLEEPDEEP bit in system control register is set, when the processor executes a Wait for Interrupt or Wait for Event instruction, or upon completing execution of an exception handler if sleep on exit bit in the system control register is set. The device exits deep sleep mode depending upon the mechanism that caused it to enter the deep sleep mode. Additionally, the Wake-Up Interrupt Controller can also wake the processor from deep sleep upon detecting an interrupt if DEEPSLEEP bit SCR register is set. When an exit event occurs, hardware brings the system clock back to the clock source and frequency it had at the onset of deep sleep mode before enabling the clocks that were disabled.