This slide provides a brief explanation of the operation of a frequency synthesizer. The RF synthesizer uses a reference frequency, typically a very stable reference from a temperature compensated crystal oscillator (TCXO), or similar source. That reference frequency may or may not be divided down internally depending on the frequency to be input to the phase frequency detector. The phase frequency detector also receives input from the VCO output after going through a divider. For the STuW81300, that divider value is determined by an integer part and a fractional part as provided by the integrated 21-bit Sigma-Delta modulator. The phase frequency detector compares the two frequencies, and depending on the difference, it will output either a positive or a negative output to the charge pump, causing the voltage out of the charge pump to either increase or decrease. This voltage is fed through an external circuit called a loop filter and then into the control voltage input for the voltage-controlled oscillators (VCOs). That control voltage determines which of the four VCOs is selected, and at what frequency the VCO will oscillate. The phase locked loop will quickly stabilize or “lock” to a very accurate and stable frequency. The lock time for the STuW81300 is typically around 90 µS. The STuW81300 has logic compatibility of 1.8 V to 3.3 V for the logic interface, and is controlled and configured via an SPI bus. If for some reason an external VCO is needed to bypass the internal VCOs, just using the PLL portion of the device, an external VCO input on the STuW81300 allows for this functionality. Additionally, it is possible to switch between the external and internal VCOs.